Embodiments of the present invention relate to a system having multiple application computer circuits, wherein one or more of the application computer circuits may function as a trace receiver to debug other application computer circuits in the system.
Contemporary computers, smart phones, and other electronic devices are highly complex systems having multiple application computer circuits that function under the direction of an operating system. These application computer circuits may, for example, be CPUs capable of executing different user application software in parallel. These user applications include a wide variety of tasks related to business applications, content access, entertainment, education, simulation, product engineering, and other user applications. Due to the complex nature of these systems, it is difficult to a) debug or verify the operation of the system that contains the application computer circuits, b) maximize the system's performance, and c) minimize the system's power consumption. Software complexity, real time interrupts, direct memory access (DMA), cache hits and misses, and data exchange between application processors further complicate the debug and verification challenge. Providing visibility into such a system's operation dramatically improves the ability to both debug and verify the system's operation. This visibility is often provided by tracing certain aspects of the system's operation. A trace circuit that records real time operation of an application computer circuit provides this capability. The trace circuit typically includes a trace receiver and a trace memory to store recorded data for subsequent analysis.
A trace receiver typically records trace data generated in real time by one or more trace sources in an encoded format, which may be referred to as trace information. These sources may generate a substantial quantity of trace data during normal operation providing information describing operation of the system containing the application computer circuit(s). The trace receiver typically stores the trace information in a trace buffer or memory that may is circular in nature. Once the trace buffer is full, trace recording either stops or new trace information is recorded over the oldest previously recorded trace information. The recorded trace information may be subsequently used by a host computer to debug or verify operation of the system.
FIG. 1A is a prior art diagram of a computer system 100 coupled to an external debug/trace probe 108 and host computer 110 of the prior art. Debug/trace probe 108 is not part of the system being analyzed. System 100 includes device 104, memory 102, and debug and trace interfaces coupling it to probe 108. An Integrated Development Environment (IDE) application on host computer 110 is used to debug or verify operation of system 100. Probe 108 stores the trace information in a trace buffer or memory 106. This method advantageously separates system memory 102 from trace memory 106. However, since trace information is transmitted from system 100 to probe 108, the bandwidth of this interface may be limited by the method of transmission and interface loading.
FIG. 1B is another prior art diagram where system 120 is coupled to debug probe 126 and host computer 110. Debug probe 126 and host computer 110 are not part of the system being analyzed. System 120 includes device 124 and memory 122. An IDE application on host computer 110 is used to debug or verify operation of system 120. When a trace operation is activated, system 120 generates trace information that is stored in memory 122. The IDE application accesses the trace information stored in memory 122 using probe 126. Since trace information is stored in memory 122, the trace bandwidth is determined by the system memory bandwidth. This configuration also limits the size of trace memory and restricts the amount of memory available to the system for applications. Furthermore, trace information transfers to and from memory 122 may restrict application memory transfers.
FIG. 1C, is a prior art diagram of system 120 coupled to host computer 110. Host computer 110 is not part of the system being analyzed. System 120 includes device 124 and memory 122 and is coupled directly to host computer 110 over a functional interface. An IDE application on host computer 110 is used to debug or verify operation of system 120. When a trace operation is activated, system 120 generates trace information that is either a) transferred in real time to host computer 110 via a high bandwidth interface or b) stored in memory 122 and subsequently transferred to host computer 110. With real time transfer of trace information, bandwidth is limited by the functional interface and the host computer. When trace information is stored in memory 122, the trace bandwidth is determined by the system memory bandwidth. This configuration also limits the size of trace memory and restricts the amount of memory available to the system for applications. Furthermore, trace information transfers to and from memory 122 may restrict application memory transfers.
In previously described systems of the prior art, components such as a host computer, debug probe, or debug/trace probe are connected to the system being analyzed. If these systems are remotely located, these external components may not be easily connected and trace functionality may be compromised. There is therefore a need to increase bandwidth of trace data throughput in a debug and verification mode to accommodate high speed application processors. There is also a need to separate system and trace memories so that they do not interfere with each other. There is a further need to make tracing of a system's operation available at all times, as some failures occur only when a system is deployed in its real operating environment. Finally, there is a need to accomplish these goals with a minimum of additional system hardware and cost.